The present invention relates to a semiconductor device having an MIS type structure, and, more specifically, to a nonvolatile semiconductor memory device and a method of manufacture thereof.
Nonvolatile semiconductor memory devices are usually formed as semiconductor integrated circuit devices. A typical example of such a device is a flash memory device that can be electrically written and erased. The flash memory device is described, for example, in Japanese Patent Laid-Open No. 276878/1987 and 219496/1991 and a paper by Kume, entitled "A 1.28 .mu.m.sup.2 Contactless Memory Cell Technology for a 3V-Only 64 Mbit EEPROM," IEDM, 1992, 92-991 to 92-993.
FIG. 10 shows a cross-sectional structure of a main portion of a proposed (comparative) flash memory device. The main part of the memory often employs a so-called stack structure. The stack structure generally refers to a structure in which a capacitor for memory is formed over an electric switch circuit. In FIG. 10, reference number 601 represents a single crystal silicon substrate, 602 a device isolation oxide film, 603 a gate oxide film (tunnel insulating film), 606 a floating gate electrode, 607 an inter-layer insulating film, 608 a control gate electrode, 610 a source, 611 a drain, 609, 612 and 613 insulating films, 614 a source interconnect, and 615 a drain interconnect.
The construction of the main part of this memory will be described in detail. The gate oxide film 603 uses a silicon oxide film about 7.5-10 nm thick, which is generally formed by thermally oxidizing a silicon substrate. The floating gate electrode 606 is made of a polycrystalline silicon film doped with a high concentration of phosphorus and has a thickness of about 50 to 200 nm. The inter-layer insulating film 607 uses a laminated film 607 of SiO.sub.2 film/Si.sub.3 N.sub.4 film/SiO.sub.2 film formed by low pressure chemical vapor deposition (LP-CVD). This laminated film 607 (of SiO.sub.2 film/Si.sub.3 N.sub.4 film/SiO.sub.2 film) is generally called an ONO film (This abbreviation "ONO film" will be used hereinafter).
A first state of information in this flash memory--for example, writing of information--is accomplished as follows. The drain 611 is set to a positive bias (for example +4V), the control gate electrode 608 is set to a negative bias (for example -10V), the source 610 is open, and the silicon substrate 601 is set to 0V. In this state, electrons stored in the floating gate electrode 606 are pulled out toward the drain 611 side, thus writing information. These voltages are each applied by using pulses about 100 microseconds long. With this method the electrons in the floating gate electrode 606 are pulled out toward the drain 611 by a Fowler-Nordheim tunneling current (hereinafter abbreviated F-N current).
A second state of information, for example, erasing of information, is done as follows. The control gate electrode 608 is set to a positive bias (for instance +10V), the silicon substrate 601 is set to a negative bias (for instance -4V), and the source 610 and the drain 611 are set to an open state. In this state, electrons are injected into the floating gate electrode 606 from the silicon substrate 601, erasing the information. These voltages are applied by using pulses about 100 microseconds long.
While the holding of information in the first state is referred to as writing and that in the second state is referred to as erasing, these states of electric charge may be called in an opposite way. Naming of these states depends on how the electric charge operates. Whatever they are called, the same states have the same problem. In the following description, the writing and erasing refer to the states of charge as described above for the purpose of facilitating the understanding of explanation. It should be noted that the description of this invention also applies to the case of a charge operation where the states of charge are called in a way opposite to this specification, by reading each of the charge states in this specification to mean the same but oppositely called state.
UK patent application No. 2,254,960 discloses an MOS device having reduced susceptibility to oxide degradation at high integration levels, the device having an improved breakdown voltage by preventing reaction between the gate oxide material and doped impurity used to improve the electrical conductivity of the gate. The gate, made of polycrystalline silicon, includes an upper polycrystalline silicon layer and a lower polycrystalline silicon layer, the lower layer having a larger grain size than the upper layer. The gate can be formed by initially forming an amorphous (lower) silicon layer and a polycrystalline silicon layer thereon, doping an impurity into the polycrystalline silicon layer and converting the amorphous silicon layer to a polycrystalline silicon layer, to form the layers having the necessary grain sizes. Illustratively, the amorphous silicon layer, converted to polycrystalline silicon, has a thickness of 20-100 nm.